Integrated circuits typically include circuit such as delay locked loops (DLLs) that provide distributed signals, e.g., clock signals, to multiple circuits. A DLL typically receives a reference clock signal from which it generates an internal clock signal, the phase of which typically depends on the reference clock signal. It may be desirable to operate a large number of circuits in synchronism with such an internal clock signal. If these circuits are driven in common, the total output load on the DLL can be very large, causing the DLL to consume a large amount of power. Consequently, integrated circuits such as merged memory logic (MML) devices, Rambus dynamic random access memories (RDRAMs), and double data rate (DDR) DRAMs often generate a plurality of synchronized DLL outputs (phases) and utilize a plurality of operation modes, such that the output signals produced by a circuit such as a DLL are selectively applied to circuits in the device to reduce unnecessary power consumption.
Proper operation of a device including a circuit such as a DLL often requires that phases produced by the circuit are accurately synchronized. However, because these output may be differently loaded, such synchronization may be problematic. Consequently, conventional DLLs may include delay circuits that can introduce delay into signals produced by the DLL.
FIG. 1 is a diagram of such a delay circuit, and FIG. 2 is a waveform diagram illustrating operations for such a circuit. When an input signal S1 to a first inverter G1 changes from a logic low level to a logic high level, a signal line n1 is driven low. However, because of charge stored in a capacitor C, the voltage at the signal line n1 falls more slowly than the corresponding rise in the input signal S1. This introduces a delay in the signal S2 generated by second inverter G2 connected to the signal line n1 with respect to the input signal S1. This delay can be reduced by opening the fuse F. However, the delay control afforded by the fuse F may be somewhat limited.